Buses are used to interconnect components and elements of digital computing systems. A bus is a collection of wires in a cable or conductive traces on a printed circuit board which transmit data, status, and control signals, and supply operating power and ground return paths. A bus between physically separate computing systems is frequently referred to as a network.
Standard buses and bus structures have become widespread in digital computing. One family of bus structures is known as Small Computer System Interface, or "SCSI". The SCSI bus structure has become standardized, as specified by document S3.131-1986 published by the American National Standards Institute in June, 1986. This bus enabled eight computer CPUs and peripherals to be interconnected, and provided a defined physical interconnect and a signaling construct enabling exchange of data between interconnecting computing/storage subsystems, etc.
One recent improvement to SCSI has been the low voltage differential bus structure. This bus structure includes a pair of signal paths or wires for each logical signal, and each path has a signaling range of only approximately 400 millivolts, e.g. 1.1 volts to 1.5 volts. Two differential signal lines can hold two binary states. The voltages (1.5 v, 1.1 v) represent one state while the voltages (1.1 v, 1.5 v) represent the opposite binary state. While the voltages in this example are not absolute, it is a characteristic of such systems that the voltage difference between the two lines (0.4 v) is much smaller than the average voltage on the two lines (e.g. 1.3 v). This very narrow signaling range presents certain unique design requirements and challenges for interface circuits supporting connection to this bus structure. Most existing SCSI systems use a single bus path for signaling instead of differential signal pairs. In such a "single-ended" system, a voltage of greater than e.g. 1.9 v represents one binary logic state while a voltage level of less than 1.1 volt represents the other binary logic state.
A multi-user (multi-drop) communication bus, such as low voltage differential SCSI, requires a mechanism for determining that the bus is idle. That is to say, a signal condition must be present indicating to all attached users that the bus is idle and not being driven by a user at a particular moment. For some commonly used buses, this mechanism is implemented by providing a weak bias or voltage offset on the bus during idle. When all of the users or drops are at a high impedance, this bias condition enables the idle bus to have a known state, known as "negated state", and the bias is known as a "negation bias".
One drawback from use of a weak bias is that the bus winds up with asymmetric drive requirements. To reverse the state of the bus, a drive signal must have a strength great enough to overcome the negation bias as well as drive a reliable signal down the transmission line. To switch back to negation requires a weaker signal, since the negation bias now aids the signal rather than opposing it.
Prior approaches have included a current source and sink driver pair for signaling (FIG. 4A, I1/I3). One common mode component resulting from tolerances present in the signal source/sink driver pair I1/I3 is a differential offset voltage which is graphed in FIG. 2, graphs A and B. An additional bias current negation source/sink pair (FIG. 4A, I2/I4) was also provided. This pair was selectively enabled specifically to counteract the bias current. While the bias current negation source and sink pair are designed to be closely matched, in practice, tolerances are present and switching the pair on and off results in a common mode ripple (time varying) component.
In addition, an on-off manner of operation of the bias current negation source/sink pair in accordance with the prior art resulted in a time varying, common mode voltage component (FIG. 2, graph C). The drawback of the prior approach becomes more clearly understood and appreciated by referring to the graphs of FIG. 3. FIG. 3 graph A shows a signaling sequence which begins with a bus idle condition, followed by a bus acquisition interval, followed by high speed data, followed by a bus release interval, and finally a return to bus idle.
With reference to FIG. 4A, the conditions for symmetrical bus drive voltages are: EQU assertion voltage=negation voltage,
or EQU (I1+Ierr1+I2+Ierr2)Z/2-Vbias=(I1+Ierr1)Z/2+Vbias,
where EQU Ierr1=(I3-I1)/2 EQU Ierr2=(I4-I2)/2.
Simplifying, EQU (I2+Ierr2)Z/2=2 Vbias.
The nominal setting for I2 is I2=2Vbias/(Z/2), so the error term Ierr2 (mismatch of I2, I4) determines the assertion/negation mismatch of the bus signal. The error term creates a significant problem because it is only present when I2 and I4 are being driven (during data assertions in the prior art, for example). Thus, when I2 and I4 are driven during high speed data, a time varying common mode error signal is added onto the bus. This error signal is further explained by reference to the following table 1 which explains operation of the FIG. 4A circuit in light of the FIG. 3 signal sequence:
TABLE 1 ______________________________________ Float Active As- Ne- Active Float Nega- Nega- As- Ne- Active Float tion tion sert gate Assert Negation Negation ______________________________________ I1/I3 0ma +4ma -4ma -4ma +4ma -4ma 0ma I2/I4 0ma 0ma +4ma 0ma +4ma 0ma 0ma Term -2ma -2ma -2ma -2ma -2ma -2ma -2ma bus: -2ma -6ma +6ma -6ma +6ma -6ma -2ma ______________________________________
To summarize the operation of the FIG. 4A driver, during a float operation, all switches are open. During a negate condition, switches S1N and S3N are closed. During an assert condition, switches S1A, S3A, S2 and S4 are closed, and currents I2 and I4 are twice the negation bias current. While the bus appears to be balanced, the bias current negation I2/I4 source-sink driver effectively injects a time varying common mode voltage shown in FIG. 3 graph C. This voltage is particularly objectionable during high speed data transfer, because it is not canceled by the terminations at the end of the bus and results in reflections and standing waves which may interfere with the integrity of the high speed data, particularly in the case of low voltage differential high speed data over e.g. a SCSI bus structure.